The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for addressing coupled noise-based violations with buffering in a batch environment.
Modern day electronics include components that use integrated circuits. Integrated circuits are electronic circuits formed using Silicon as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, and resistors. Circuit designers use a variety of software tools to design electronic circuits that accomplish an intended task. For example, a digital circuit may be designed to accept digital inputs, perform some computation, and produce a digital output. An analog circuit may be designed to accept analog signals, manipulate the analog signals, such as my amplifying, filtering, or mixing the signals, and produce an analog or digital output. Generally, any type of circuit can be designed as an IC.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout at very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometers across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including millions of such components and wires, often referred to as nets, interconnected to form an intended electronic circuitry.
Noise is a random fluctuation in an electrical signal, which is a characteristic of all electronic circuits. Noise generated by electronic devices varies greatly, as the noise may be produced by several different effects. Eliminating noise or more specifically Noise Impact on Timing (NIOT) is a major component of achieving timing closure on larger design units after detail routing. A wire or net, i.e. a “victim net”, that contributes to path delay may have that contribution tripled by NIOT. Delta wire delay is the signal assignment propagation delay inherent in each net. This delta wire delay may increase the stage delay, i.e. the combination of all the delta wire delays for each net as well any gate delays for each component of the circuit, when NIOT is taken into account.
Accordingly, interconnect performance, taking into consideration all delay factors, is becoming increasingly dominant over transistor and logic performance in the deep submicron regime. Buffer insertion is a fundamental technology used in modern integrated circuit design methodologies to address delay factors. As gate delays decrease with increasing chip dimensions, the number of buffers required quickly rises. Furthermore, after detail routing, calculating NIOT is typically a central processing unit (CPU) intensive “batch” operation, which is dependent on 2.5D or 3D coupled parasitic analysis; delta wire delay that is a function of relative location of the coupling to the aggressor net, resistive shielding in wire, drive strength and slew of source, arrival time of source and victim signals; complex interplay determining whether signals will be switching in same timing window; and incremental recalculation of NIOT after making small updates to the design, all of which is CPU intensive.